BÜCHER VERSANDKOSTENFREI INNERHALB DEUTSCHLANDS
eBook
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Springer Nature Singapore
ISBN 9789811010736
Standardpreis
Bibliografische Daten
eBook. PDF
2017
XX, 197 p. 104 illus., 72 illus. in color..
In englischer Sprache
Umfang: 197 S.
Verlag: Springer Nature Singapore
ISBN: 9789811010736
Weiterführende bibliografische Daten
Das Werk ist Teil der Reihe: Computer Architecture and Design Methodologies
Produktbeschreibung
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
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