Debugging Systems-on-Chip

This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly.  Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors.  The authors' novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug flow to be used during the design of an SOC, and customizable off-chip debugger software. Coverage includes an evaluation of the efficiency and effectiveness of the CSAR approach and its supporting infrastructure, using six industrial SOCs and an illustrative, example SOC model.  The authors also quantify the hardware cost and design effort to support their approach.   . Describes trends in embedded system design that make the design of SOCs complex and error-prone; . Analyzes four key requirements for debugging a modern, silicon SOC implementation and identifies nine factors that complicate meeting these debug requirements; . Uses communication control for debugging SOCs, which can be used with most on-chip SOC communication protocols in use today; . Uses communication control to (re)create a particular transaction order and demonstrates that this is helpful in the localization of errors in a SOC implementation; . Demonstrates the necessity of extracting locally- and globally-consistent states during SOC debug and guarantees by design that they are so; . Uses a fast and scalable event distribution interconnect, which connects on-chip monitors and protocol specific instruments); . Evaluates benefits and costs of the CSAR approach using six industrial SOC designs and an example SOC model.