Erschienen: 29.06.2017 Abbildung von Mehta | ASIC/SoC Functional Design Verification | 1st ed. 2018 | 2017 | A Comprehensive Guide to Techn...


ASIC/SoC Functional Design Verification

A Comprehensive Guide to Technologies and Methodologies

1st ed. 2018 2017. Buch. xxxi, 328 S. 15 s/w-Abbildungen, 160 Farbabbildungen, 50 Farbtabellen, Bibliographien. Hardcover

Springer. ISBN 978-3-319-59417-0

Format (B x L): 15,5 x 23,5 cm

Gewicht: 701 g

In englischer Sprache


This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.


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